EDN

Logic analyzer creates multichannel eye diagrams

Purists may argue that you can't create true eye diagrams by using the eye-scan mode of Agilent's new 68-channel, 300/600-MHz (state), 1.2-GHz (timing)/4-GHz (timing-zoom), deep-memory logic-analysis ...
Electronic Design

Eye-Diagram Analysis Speeds DDR SDRAM Validation

Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to ...
Electronic Design

Test & Measurement: Multigigabit/s Analyzers Combine BER Testing, Eye-Diagram Analysis

Bit-error-rate (BER) pattern generation and analysis merges with eye-diagram analysis on the BertScope 100-Mbit/s to 7.5-Gbit/s 7500A and 100-Mbit/s to 12.5-Gbit/s ...
EDN

Choosing the Right Mixed-Signal Test Equipment

At one time the boundaries between analog and digital designs were clearly defined. As the complexity and performance levels of systems have increased, maintaining those boundaries has become more ...